1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device and, more specifically, to a synchronous semiconductor memory device in which a test mode is reset at the time of power on.
2. Description of the Background Art
In a synchronous semiconductor memory device developed in order to attain high speed accessing, operations (instructions) necessary for data reading or writing are all performed in synchronization with a clock (external clock signal) applied externally with a stable period.
A conventional synchronous semiconductor memory device will be described with reference to FIG. 21. A synchronous semiconductor memory device 9000 shown in FIG. 21 includes a control signal buffer 101, an internal clock generating circuit 102, an address buffer 103, a mode setting circuit 104, an act generating circuit 106, a precharge generating circuit 105, a POR generating circuit 100 and a plurality of banks (in FIG. 21, banks B0, B1, B2 and B3).
Banks B0, B1, B2 and B3 each include a row system control circuit, a word driver, a sense amplifier and an IO gate, not shown. Each bank is capable of activating a word line, reading data, writing data and inactivating a word line, independent from each other.
The memory cell array, not shown, includes a plurality of memory cells arranged in a matrix of rows and columns, and each memory cell is connected to a crossing between a word line provided corresponding to the row direction and a bit line pair provided corresponding to the column direction.
Control signal buffer 101 receives external control signals (external row address strobe signal /RAS, external column address strobe signal /CAS, external write enable signal /WE and so on), and outputs corresponding internal control signals. In the following description, internal control signals ZCS, ZRAS, ZCAS and ZWE denote internal signals corresponding to and in phase with an external chip select signal /CS, external row address strobe signal /RAS, external column address strobe signal /CAS and external write enable signal /WE, which are external control signals, respectively. Internal control signals CS, RAS, CAS and WE denote internal signals of opposite phase to internal control signals ZCS, ZRAS, ZCAS and ZWE, respectively.
Internal clock generating circuit 102 takes in an external clock signal EXTCLK and outputs an internal clock signal CLK for controlling internal operation.
Address buffer 103 takes in an externally applied external address signal A and outputs an address signal (which will be referred to as ADD0, ADD1, . . . , ADD7). The external address signal A includes a row address signal and a column address signal time divisionally multiplexed. Further, address buffer 103 includes a bank address decoder, not shown, which decodes the address signal A and outputs a bank decode signal designating a corresponding bank.
Act generating circuit 106 outputs an act start signal for activating a designated bank, in response to an externally input act command. Precharge generating circuit 105 outputs a precharge start signal for inactivating a designated bank, in response to an externally input precharge command.
Mode setting circuit 104 sets a specific operation mode or a test mode in response to an external signal, which will be described later. Thus, it is possible to set various operation modes or test modes including a CAS latency CL and burst length BL.
POR generating circuit 100 outputs, for a prescribed period after power on, a power on reset signal ZPOR based on an external power supply voltage EXTVDD. Mode setting circuit 104 is reset upon reception of the power on reset signal ZPOR.
Normal operation of the conventional synchronous semiconductor memory device 9000 shown in FIG. 21 from power on until it enters idle state will be described with reference to a timing chart of FIG. 22.
In FIG. 22, (A) represents internal clock signal CLK, (B) represents an internal control signal (clock enable signal) CKE, (C) represents internal control signal ZCS, (D) represents internal control signal ZRAS, (E) represents internal control signal ZCAS and (F) represents internal control signal ZWE, respectively. Further, (G) represents address signal A, (H) represents bank decode signal BA, (I) represents power supply voltage EXTVDD, and (J) represents power on reset signal ZPOR, respectively.
After power on (time t0), power supply voltage EXTVDD rises. At a time point (time t1) when external power supply voltage EXTVDD attains to a prescribed level, the power on reset signal ZPOR is output from POR generating circuit 100, and the synchronous semiconductor memory device is internally reset.
Thereafter, a stable clock state of 200 .mu.s is kept, so that internal voltage system is stabilized. Thereafter, a precharge all command PREA (specified by internal control signals ZRAS and ZWE at the L level and internal control signal ZCAS at the H level) is executed on all the banks. After the lapse of a tRP period (normally, 30 ns), an auto refresh command REFA (specified by internal control signals ZRAS and ZCAS at the L level and internal control signal ZWE at the H level) is executed eight times or more with the cycle of tRC period (normally, 80 ns).
Thereafter, a mode register set command MRS (specified by setting internal control signals ZRAS, ZCAS and ZWE to the L level and by inputting address signal A) is input, so that an operation mode of a circuit such as CAS latency CL or burst length BL is set.
Mode setting circuit 104 which operates in response to the mode register set command will be briefly described with reference to FIG. 23.
The conventional mode setting circuit 104 shown in FIG. 23 includes a mode detecting circuit 115, a normal mode setting circuit 124 and a test mode setting circuit 125.
Normal mode setting circuit 124 includes a normal mode register 116 and a normal mode decoder 117. Test mode setting circuit 125 includes a test mode register 118 and a test mode decoder 119.
Mode detecting circuit 115 is responsive to the mode register set command and address signal ADD7 and outputs a signal for operating a normal mode register 116 or a test mode register 118, which will be described later. Address signal ADD7 is a key signal for entering the test mode.
Here, the test mode refers to an operation mode employed for efficiently evaluating and analyzing the synchronous semiconductor memory device, and it is set by a procedure which is not used in actual use (more specifically, address signal ADD7 is fixed at the L level).
Normal mode setting circuit 124 outputs various mode signals (CAS latency CL, burst length BL, . . . ) in response to address signals ADD0, . . . , ADD6 at the time of input of the mode register set command.
Test mode setting circuit 125 outputs various test mode signals in response to address signals ADD0, ADD1 and ADD7 at the time of input of the mode register set command.
Here, when the address signal ADD7 is at the L level, address signals ADD0, . . . , ADD6 will be a decode signal for selecting a specific one mode among a plurality of normal modes. When address signal ADD7 is at the H level, address signals ADD0 and ADD1 will be a decode signal for selecting any one of a plurality of test modes.
Structure of the mode detecting circuit 115 will be briefly described with reference to FIG. 24.
Referring to FIG. 24, mode detecting circuit 115 includes an NAND circuit 1, NOR circuits 2 and 5, and inverter circuits 3, 4, 6 and 7. When input of the mode register set command (specified by internal control signals CS, RAS, CAS and WE at the H level) is detected, NAND circuit 1 outputs a signal MR which is at the L level.
NOR circuit 2 receives at its inputs the signal MR and address signal ADD7. NOR circuit 5 receives at its inputs the signal MR and the ground potential.
Inverter circuit 3 inverts an output signal from NOR circuit 2, and outputs an inverted normal mode set signal ZSNM. Inverter circuit 4 inverts the inverted normal mode set signal ZSNM, and outputs a normal mode set signal SNM.
Inverter circuit 6 inverts an output signal from NOR circuit 5 and outputs an inverted test mode set signal ZSTM. Inverter circuit 7 inverts the inverted test mode set signal ZSTM and outputs a test mode set signal STM.
A register constituting normal mode register 116 and test mode register 118 will be described with reference to FIG. 25.
A register R1 shown in FIG. 25 is a latch type register and it includes inverter circuits 11, 12 and 13, gate circuits 14 and 15, and an NOR circuit 16.
Inverter circuit 11 inverts a signal at input node N1 and outputs the inverted signal to NOR circuit 16. Gate circuit 14 inverts, in response to signals at input nodes N3 and N4, a signal received from input node N2 and outputs the inverted signal to node Z1. NOR circuit 16 receives signals from inverter circuit 11 and node Z1. Gate circuit 15 inverts, in response to signals at input nodes N3 and N4, an output signal from NOR circuit 16 and outputs the result to node Z1. Inverter circuit 12 inverts the signal at node Z1 and outputs the result to output node N5. Inverter circuit 13 inverts an output signal from inverter circuit 12 and outputs the result to output node N6.
Normal mode register 116 includes resistors R1 corresponding to address signals ADD0, . . . , ADD6, respectively. Register R1 corresponding to address signal ADDi (where i=0, . . . , 6) receives at an input node N1, the power on reset signal ZPOR and at input node N2, the corresponding address signal ADDi. Further, the register receives at an input node N3, the inverted normal mode set signal ZSNM, and at input node N4, the normal mode set signal SNM. A signal NADDi is output from an output node N5, and its inverted signal, an inverted signal ZNADDi is output from an output node N6 (hereinafter the signals will be generally referred to as NADDi and inverted signal ZNADD).
Test mode register 118 includes registers R1 corresponding to address signals ADD0 and ADD1, respectively. Register R1 corresponding to address signal ADDi (where i=0, 1) receives at input node N1, the power on reset signal ZPOR, and at input node N2, the corresponding address signal ADDi. Further, the register R1 receives at input node N3, the inverted test mode set signal ZSTM, and at input node N4, receives the test mode set signal STM. A signal TADDi is output from output node N5, and its inverted signal, an inverted signal ZTADDi is output from output node N6 (hereinafter, these signals will be generally referred to as signal TADD and inverted signal ZTADD).
Further, test mode register 118 includes a register corresponding to address signal ADD7. The register corresponding to address signal ADD7 has the same circuit structure as register R1 shown in FIG. 25, with an inverter circuit 13 (output node N6) removed (hereinafter, the register will be referred to as register R2). Register R2 receives, at input node N1, the power on reset signal ZPOR, at input node N2, address signal ADD7, at input node N3, inverted test mode set signal ZSTM and at input node N4, test mode set signal STM. Test mode enable signal TME is output from output node N5 of register R2.
Structure of the test mode decoder 119 will be briefly described with reference to FIG. 26.
Test mode decoder 119 shown in FIG. 26 includes NAND circuits 21, 22, 23 and 24, and inverter circuits 25, 26, 27 and 28. The signal TADD, inverted signal ZTADD and test mode enable signal TME output from test mode register 118 are input to respective input nodes of NAND circuits 21, . . . , 24. Test mode signals TM1, TM2, TM3 and TM4 are output from inverter circuits 25, 26, 27 and 28, respectively.
Normal mode decoder 117 has the same structure as test mode decoder 119 and outputs a mode signal in response to a combination of the signal NADD and the inverted signal ZNADD output from normal mode register 116.
Relation between operations of normal mode setting circuit 124 and test mode setting circuit 125 will be described with reference to the timing chart of FIG. 27.
In FIG. 27, (A) represents internal clock signal CLK, (B) represents internal control signal CS, (C) represents internal control signal RAS, (D) represents internal control signal CAS, (E) represents internal control signal WE, (F) represents address signal ADD7, (G) represents normal mode set signal SNM and (H) represents test mode set signal STM.
As shown in FIG. 27, if address signal ADD7 is at the H level when mode register set command MRS is input (time t0), test mode set signal STM attains to the H level while the normal mode set signal SNM is at the L level, and therefore test mode register 118 is set while the content of normal mode register 116 is protected.
If address signal ADD7 is at the H level when mode register set command MRS is input (time t1), normal mode set signal SNM and test mode set signal STM both attain to the H level. In this case, inlet of register R1 of normal mode register 116 is opened, and addresses ADD0, . . . , ADD6 are taken in. Thus, the signal NADD and the inverted signal ZNADD are generated. As shown in the circuit diagram, normal mode register 116 is a latch type circuit, and taking of a signal is performed only by the mode register set command.
The address signals which are taken in are decoded by normal mode decoder 117 and provide information related to mode signal BL, CL and so on. Meanwhile, since address signal ADD7 at the L level is taken in by register R2, test mode enable signal TME is reset, and the test mode is reset (exit).
In actual use (normal mode), address signal ADD7 is fixed at the L level when mode register set command is input, so that entrance to test mode is prevented.
As described above, the conventional synchronous semiconductor memory device 9000 includes a test mode setting circuit 125 for testing before delivery, and in the actual use, power on reset signal ZPOR is used for resetting, so as to prevent erroneous entrance to the test mode.
The power on reset signal ZPOR, however, may not sufficiently be generated at the time of power on, dependent on the condition of rise of the power supply. Therefore, resetting by the power on reset signal ZPOR signal is not very reliable.
Meanwhile, the conventional semiconductor memory device 9000 includes normal mode setting circuit 124 and test mode setting circuit 125, and operations of these circuits are controlled by combination of address signals at the time of input of the mode register set command. Though the combinations of the addresses are not open in the actual use, it is possible that the test mode is erroneously entered if the reset should be insufficient.
In fact, there are computer systems which support both EDO DRAM (Extended Data Out Dynamic Random Access Memory) and the synchronous semiconductor memory device. In such a system, it is possible that an unnecessary signal is applied to the synchronous semiconductor memory device in an operation of checking the memory.
Therefore, there still remains possibility of erroneous entrance to the test mode in the actual use. Therefore, in the conventional synchronous semiconductor memory device 9000, the test mode is reset by the mode register set command in the normal mode. However, when the test mode involves variation in internal potential, a time period of at least several hundreds ns is necessary from the cancellation of the test mode until the internal voltage returns to the set value. Therefore, if an operation instruction such as an act command is input to the synchronous semiconductor memory device 9000 immediately after the execution of the mode register set command, the synchronous semiconductor memory device 9000 may possibly malfunction.